-------------------------------	-----------------------------------------	-------------------------------------------------
-- model supplier:	Johan Sandstrom	310.977.9435
--		johan@sandstrom.org
-- project:	PreSynth.
-- description:	A VHDL priority arbiter design
-- filename:	Source.vhd
-- yyyy/mm/dd	modifier	Description of change
----------------	-------------	-------------------------------------------------
-- 1997/10/24	johan	Small testcase.
-------------------------------	-----------------------------------------	-------------------------------------------------

-- positive
-- buffer
-- file
-- alias
-- initial value
-- rising_edge
-- assert

library std;
 use std.textio.all;
library ieee;
use ieee.std_logic_1164.all;

entity source_PS is
--generic(width : positive := 4); MSG_005
  generic(width : integer := 4);
  port (clk                   : in        std_logic;
            reset               : in        std_logic;
            cntl_en          : out      std_logic;
            ad_bus_in    : in         std_logic_vector(23 downto 0);
--         ad_bus_out  : buffer std_logic_vector(23 downto 0); MSG_002
            ad_bus_out  : out      std_logic_vector(23 downto 0);
            requests        : in         std_logic_vector(width-1 downto 0);
--         grants            : buffer  std_logic_vector(width-1 downto 0); MSG_002
            grants            : out      std_logic_vector(width-1 downto 0);
            data               : out       std_logic_vector(7 downto 0));
end source_PS;

architecture bhv of source_PS is

  file read_file : text is in "somefile.vhd"; -- ERR_001

--alias address_in : std_logic_vector(7 downto 0) is
--                                           ad_bus_in(7 downto 0); MSG_010
--alias address_out : std_logic_vector(7 downto 0) is
--                                           ad_bus_out(7 downto 0); MSG_010

--alias data_in : std_logic_vector(15 downto 0) is
--                                     ad_bus_in(23 downto 8); MSG_010

--alias data_out : std_logic_vector(15 downto 0) is
--                                     ad_bus_out(23 downto 8); MSG_010

component org_comp
  port (clk     : in   std_logic;
            din    : in   std_logic_vector(7 downto 0);
            dout : out std_logic_vector(7 downto 0));
end component;

begin

  i1 : org_comp
    port map(clk    => clk,
                     din    => ad_bus_in(17 downto 10),
                     dout => data);

  org_process : process
-- variable lo : std_logic_vector(width-1 downto 0) := (others => '0'); WRN_002
    variable lo : std_logic_vector(width-1 downto 0);
-- variable hi : std_logic_vector(7 downto 0)            := (others => '1'); WRN_002
    variable hi : std_logic_vector(7 downto 0);
  begin

-- wait until rising_edge(clk); MSG_003
    wait until clk='1' ;

    grants            <= (others => '0');
    cntl_en          <= '1';
-- address_out <= (others => '0'); MSG_010
    ad_bus_out(7 downto 0) <= (others => '0');
-- data_out       <= (others => '1'); MSG_010
    ad_bus_out(23 downto 8) <= (others => '1');

    if reset = '1' then
     grants           <= (others => '0');
     ad_bus_out <= (others => '0');
   elsif reset = '0' then
     if requests(3) = '1' then
       grants(3) <= '1';
    elsif requests(2) = '1' then
       grants(2) <= '1';
    elsif requests(1) = '1' then
       grants(1) <= '1';
    elsif requests(0) = '1' then
       grants(0) <= '1';
--  elsif requests = lo and address_in /= hi then MSG_010
     elsif requests = lo and ad_bus_in(7 downto 0) /= hi then
       cntl_en          <= '0';
--    address_out <= (others => '1'); MSG_010
       ad_bus_out(7 downto 0) <= (others => '1');
       ad_bus_out(23 downto 8) <= (others => '0');
--  elsif requests = lo and address_in = hi then MSG_010
     elsif requests = lo and ad_bus_in(7 downto 0) = hi then
--    data_out <= data_in; MSG_010
--    data_out <= ad_bus_in(23 downto 8); MSG_010
       ad_bus_out(23 downto 8) <= ad_bus_in(23 downto 8);
     else
        -- synopsys translate_off
       assert false report "REQUESTS is_x" severity error;
        -- synopsys translate_on
     end if;
   end if;
 end process org_process;

  -- synopsys translate_off
  assert false report "Everything must be ignored in here. " &
                                   "Like out in ASSERT end if etc;"
                                   severity error; -- synopsys translate_on

  -- synopsys synthesis_off
  assert false report "Synthesis_off this assert" severity note;
  -- synopsys synthesis_on

end bhv;

-- ERR_001 : File constructs not supported by synthesis tools,
-- *** YOU MUST FIX YOUR CODE ***

-- WRN_002 : Initial values for signals and variables get removed.
-- You must initialize your circuit through hardware.

-- MSG_001 : The comments to lines-of-code is '45 %' (% := '--'/;)
-- Quality comments should be > 20 % of your code.

-- MSG_002 : Mode buffer changed to mode out.
--

-- MSG_003 : Rising_edge changed to = '1'.
--

-- MSG_005 : Positive changed to integer.
--

-- MSG_007 : Synopsys translate_off/on placed around assert.
--

-- MSG_010 : Alias constructs not supported by synthesis tools.
--