-------------------------------  -----------------------------------------  ------------------------------------------------- 
-- model supplier: Johan Sandstrom 310.977.9435
-- johan@sandstrom.org 
-- project: PreSynth.
-- description: A VHDL priority arbiter design.
-- filename: source.vhd
-- yyyy/mm/dd modifier Description of change 
----------------  -------------  ------------------------------------------------- 
-- 1997/10/24 johan Small Testcase 
-------------------------------  -----------------------------------------  ------------------------------------------------- 
-- positive
-- buffer
-- file
-- alias
-- initial value
-- rising_edge
-- assert

library std; use std.textio.all;
library ieee; use ieee.std_logic_1164.all;

entity source is
  generic(width : positive := 4);
  port (clk                  : in        std_logic;
            reset              : in        std_logic;
            cntl_en         : out      std_logic;
            ad_bus_in    : in        std_logic_vector(23 downto 0);
            ad_bus_out : buffer std_logic_vector(23 downto 0);
            requests       : in         std_logic_vector(width-1 downto 0);
            grants           : buffer  std_logic_vector(width-1 downto 0);
            data               : out      std_logic_vector(7 downto 0));
end source;

architecture bhv of source is

  file read_file : text is in "somefile.vhd"

  alias address_in : std_logic_vector(7 downto 0) is
                                             ad_bus_in(7 downto 0);

  alias address_out : std_logic_vector(7 downto 0) is
                                             ad_bus_out(7 downto 0);

  alias data_in : std_logic_vector(15 downto 0) is
                                       ad_bus_in(23 downto 8);

  alias data_out : std_logic_vector(15 downto 0) is
                                       ad_bus_out(23 downto8);

  component org_comp
    port (clk    : in   std_logic;
             din    : in   std_logic_vector(7 downto 0);
             dout : out std_logic_vector(7 downto 0));
  end component;

begin

  i1 : org_comp
    port map (clk     => clk,
                      din    => ad_bus_in(17 downto 10),
                      dout => data);

  org_process : process
    variable lo : std_logic_vector(width-1 downto 0) := (others => '0');
    variable hi : std_logic_vector(7 downto 0)            := (others => '1');
  begin

    wait until rising_edge(clk);

    grants            <= (others => '0');
    cntl_en          <= '1';
    address_out <= (others =>'0');
    data_out       <= (others => '1');

     if reset = '1' then
       grants           <= (others => '0');
       ad_bus_out <= (others => '0');
    elsif reset = '0' then
      if requests(3) = '1' then
        grants(3) <= '1';
     elsif requests(2)= '1' then
       grants(2) <= '1';
     elsif requests(1) = '1' then
       grants(1) <= '1';
     elsif requests(0) = '1' then
       grants(0) <= '1';
     elsif requests = lo and address_in /= hi then
       cntl_en <= '0';
       address_out <= (others=> '1');
       data_out <= (others => '0');
     elsif requests = lo and address_in = hi then
       data_out <= data_in;
     else
       -- synopsys translate_off
       assert false report "REQUESTS is_x" severity error;
       -- synopsys translate_on
      end if;
    end if;
  end process org_process;

  assert false report "Everything must be ignored in here. " &
                                   "Like out in ASSERT end if etc;"
                                   severity error;

  -- synopsys synthesis_off
  assert false report "Synthesis_off this assert" severity note;
  -- synopsys synthesis_on

end bhv;